The present invention relates to a semiconductor apparatus and a manufacturing method thereof, and particularly to improvement in a switching speed and a withstand voltage of a semiconductor apparatus.
In recent years, a withstand high-voltage and a speedup in a switching speed are strongly required in a semiconductor apparatus used in, for example, a power source apparatus or a flat panel display such as a plasma display or a liquid crystal display. In order to respond to the recent requirement, a semiconductor element disclosed in JP-A-2002-246610 has an MPS (Merged Pin/Schottky Diode) structure in which a pn diode and a Schottky diode are placed in parallel inside one chip.
FIG. 5 is a top view of the semiconductor element disclosed in the above mentioned reference. Also, FIG. 6 is a sectional view taken on line A-A of the semiconductor element shown in FIG. 5. In addition to FIG. 5, an anode electrode 13 is shown in FIG. 6. In the semiconductor element 1 shown in FIGS. 5 and 6, plural P+-type silicon regions 15 are formed at equal distances in an island shape in a surface of an N-type silicon region 12 formed on an N+-type silicon layer 11. An insulating film 16 having an opening 16a is formed on an upper part of the N-type silicon region 12 including P+-type silicon regions 15a positioned in the outermost periphery of the P+-type silicon regions 15. Further, as shown in FIG. 6, the anode electrode 13 is disposed on the insulating film 16, the P+-type silicon regions 15 and the N-type silicon region 12 exposed from the opening 16a of the insulating film 16. A cathode electrode 14 is disposed on a lower surface of the N+-type silicon layer 11, that is, a surface opposite to the anode electrode 13.
In the semiconductor element 1, the insulating film 16 is formed on the upper parts of the P+-type silicon regions 15a positioned in the outermost periphery of the P+-type silicon regions 15 so that the anode electrode 13 is not in contact with the P+-type silicon regions 15a. Also, the P+-type silicon regions 15 are arranged so as to form a depletion layer 30 substantially integrated as shown in FIG. 7 at the time of applying a reverse voltage.
However, the semiconductor element 1 described above becomes the so-called pinch-off state in which depletion layers formed by a PN junction between the N-type silicon region 12 and the island-shaped P+-type silicon regions 15 under a reverse voltage application are mutually coupled and are substantially integrated. At this time, a region in which the depletion layers extending from the adjacent P+-type silicon regions 15 overlap becomes a discontinuous state and a withstand voltage reduces as compared with depletion layers extending in a continuous state. Also, the depletion layers extending from the island-shaped P+-type silicon regions 15 have a predetermined large curvature, but at the time of applying a reverse voltage, an electric field concentrates in the portion of its curvature and a reduction in a withstand voltage is caused.
An object of the invention is to provide a semiconductor apparatus for improving a switching speed and a withstand voltage, and a manufacturing method of the semiconductor apparatus.